1.Good understanding of the ASIC and FPGA design flow
2.Extensive experience in writing RTL models in Verilog HDL and Testbenches in System Verilog and UVM
3.Very good knoweldge in verification methodologies
4.Experience in鈥渋MSpired solution pvt. Ltd鈥�, Bangalore one year worked as intern and using industry standard EDA tools for the front-end design and verification
5.Verificaion Methodologies:Coverage Driven and Assertion Based Verification
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