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21EC71_Floor Planning _PPT Electronics and communication engineering module 2
- 2. Introduction • The input to the floorplanning step - output of system partitioning and design entry—a netlist. • Netlist - describing circuit blocks, the logic cells within the blocks, and their connections.
- 3. • th Te hevit se tr ab rti ingde pcod ne tr of floorplaning and placement steps for routing. •-collection of standard cells with no room set aside ye1t58for
- 4. The starting point of floorplaning and placement steps for the viterbi decoder • Small boxes that look like bricks - outlines of the standard cells. • Largest standard cells, at the bottom of the display (labeled dfctnb) - 188 D flipflops. • '+' symbols -drawing origins of the standard cells—for the D flip- flops they are shifted to the left and below the logic cell bottom left-hand corner. • Large box surrounding all the logic cells - estimated chip size. • (This is a screen shot from Cadence Cell Ensemble.)
- 5. The viterbi decoder after floorplanning and placement
- 6. The viterbi decoder after floorplanning and placement • 8 rows of standard cells separated by 17 horizontal channels (labeled 2–18). • Channels are routed as numbered. • In this example, the I/O pads are omitted to show the cell placement more clearly.
- 7. Floorplanning Goals and Objectives • The input to a floorplanning tool is a hierarchical netlist that describes – the interconnection of the blocks (RAM, ROM, ALU, cache controller, and so on) – the logic cells (NAND, NOR, D flip-flop, and so on) within the blocks – the logic cell connectors (terminals , pins , or ports) • The netlist is a logical description of the ASIC; • The floorplan is a physical description of an ASIC. • Floorplanning is a mapping between the logical description (the netlist) and the physical description (the floorplan). The Goals of Floorplanning are to: • Arrange the blocks on a chip, • Decide the location of the I/O pads, • Decide the location and number of the power pads, • Decide the type of power distribution, and • Decide the location and type of clock distribution. Objectives of Floorplanning – To minimize the chip area To minimize delay. Measuring area is straightforward,
- 8. Measurement of Delay in Floor planning •Floor planning - To predict interconnect delay by estimating interconnect length.
- 9. Measurement of Delay in Floor planning
- 10. Measurement of Delay in Floor planning (contd.,) • A floorplanning tool can use predicted-capacitance tables (also known as interconnect-load tables or wire-load tables ). • Typically between 60 and 70 percent of nets have a FO = 1. • The distribution for a FO = 1 has a very long tail, stretching to interconnects that run from corner to corner of the chip. • The distribution for a FO = 1 often has two peaks, corresponding to a distribution for close neighbors in subgroups within a block, superimposed on a distribution corresponding to routing between subgroups.
- 11. Measurement of Delay in Floor planning (contd.,) • We often see a twin-peaked distribution at the chip level also, corresponding to separate distributions for interblock routing (inside blocks) and intrablock routing (between blocks). • The distributions for FO > 1 are more symmetrical and flatter than for FO = 1. • The wire-load tables can only contain one number, for example the average net capacitance, for any one distribution. • Many tools take a worst-case approach and use the 80- or 90-percentile point instead of the average. Thus a tool may use a predicted capacitance for which we know 90 percent of the nets will have less than the estimated capacitance. 166
- 12. • Repeat the statistical analysis for blocks with different sizes. For example, a net with a FO = 1 in a 25 k-gate block will have a different (larger) average length than if the net were in a 5 k-gate block. • The statistics depend on the shape (aspect ratio) of the block (usually the statistics are only calculated for square blocks). • The statistics will also depend on the type of netlist. For example, the distributions will be different for a netlist generated by setting a constraint for minimum logic delay during synthesis—which tends to generate large numbers of two-input NAND gates—than for netlists generated using minimum-area constraints. Measurement of Delay in Floor planning (contd.,)