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21EC71_Module-2_Routing PPT Electronics and communication engineering module 2
- 1. MODULE 2 Floor planning and placement: Goals and objectives, Measurement of delay in Floor planning, Floor planning tools, Channel definition, I/O and Power planning and Clock planning. Placement: Goals and Objectives, Min-cut Placement algorithm, Iterative Placement Improvement,Time driven placement methods, Physical Design Flow. Routing: Global Routing: Goals and objectives, Global Routing Methods, Global routing between blocks, Back annotation. Text Book 1
- 2. ROUTING
- 3. • Once the designer has floorplanned a chip and the logic cells within the flexible blocks have been placed, it is time to make the connections by routing the chip. • This is still a hard problem that is made easier by dividing it into smaller problems. • Routing is usually split into global routing followed by detailed routing .
- 4. Global Routing Goals : • The goal of global routing is to provide complete instructions to the detailed router on where to route every net. Objectives of global routing : • Minimize the total interconnect length. • Maximize the probability that the detailed router can complete the routing. • Minimize the critical path delay. • The input to the global router is a floorplan that includes the locations of all the fixed and flexible blocks. • The placement information for flexible blocks and the locations of all the logic cells.
- 5. • Sequential global routing Perhaps the most straightforward strategy for routing is to select a specific net order and then to route nets sequentially in that order. • However, this sequential approach often leads to a poor routing result, because an earlier routed net might block the routing for its subsequent nets. Therefore, the quality of the routing solution greatly depends on the net ordering. • Algorithms can be classified into sequential and concurrent approaches,
- 6. Sequential routing •One of the approach for global routing picks up each net in turn and calculates the shortest path using tree algorithms also known as Sequential routing •As this algorithm proceeds, some channels will become more congested since they hold more nets than others. •There are two different ways that a global router handles this congestion problem. 1. Using order-independent and 2. Order-dependent routing.
- 7. Routing for different net orderings, (a) One layer routing case with two two-pin nets 1 and 2, (b) Net ordering of 1 followed by 2 and it is inferior solution, (c) A better solution by net ordering 2 followed by 1.
- 8. There are some popular net-ordering schemes as follows: (1) Order the nets in the ascending order according to the number of pins within their bounding boxes. (2) Order the nets in the ascending or descending order of their lengths if routability is the most critical issue. Research shows that routing shorter nets first often leads to better routability. (3) Order the nets on the basis of their timing criticality. Other method hierarchical (top down and bottom up)
- 9. Concurrent routing • The major drawback of the sequential approach is that it suffers from the net ordering problem. • In any net ordering scheme, it is more difficult to route the nets that are processed later, because they are subjected to more blockages. • Moreover, when the sequential routing does find a feasible solution, we do not know whether or not this solution is optimal or how far it is from the optimal solution. • One popular concurrent approach is to formulate global routing as a 0-1 integer linear programming algorithm
- 10. Global Routing Between Blocks Global routing for a cell-based ASIC formulated as a graph problem. (a) A cell-based ASIC with numbered channels. (b) The channels form the edges of a graph. (c) The channel-intersection graph. Each channel corresponds to an edge on a graph whose weight corresponds to the channel length.
- 11. Back-annotation • Used in connection to netlist simulations and STA where the propagation delay(s) through each cell in the netlist is overridden by the delay value(s) specified in a special file called sdf (synopsys delay format) file. • The process of putting delays from a given source for the cells in a netlist during netlist simulation is called Back Annotation. • Normally the values of the delays corresponding to each cell in the netlist would come from the simulation library i.e verilogmodel of library cells. • But those delays are not the actual delays of cells, as each of them is instantiated in a netlist in different surroundings, different physical locations, different loads, different fan in.
- 12. • The delay of two similar cells in the netlist at two different physical locations in a chip can be significantly different depending upon above said factors. • Therefore in order to have actual delays for the cells in your netlist, an SDF is written out, by a EDA tool can be a synthesis tool or a layout tool etc.. • which contains the delays of each instance of each library cell in the netlist, under the circumstances the cell is in. • During simulations or Static Timing Analysis, each cell in the netlist gets its correponding delay read, or more technically 'annotated' from the SDF file.