The document discusses dynamic and pass-transistor logic circuits. It begins with references to papers on dynamic CMOS logic, differential cascode voltage switch logic, and pass-transistor logic. It then provides overviews of various dynamic CMOS logic circuits including latches, domino logic, and NORA logic. Other logic styles discussed include cascode voltage switch logic, differential cascode voltage switch logic, and pass-transistor logic. The document describes the operation and advantages of these different logic families. It also discusses formal methods for deriving complementary pass-transistor logic and double pass-transistor logic circuits.
The document summarizes the operation of a CMOS transmission gate (TG). A TG consists of a parallel nMOS and pMOS transistor that act as a bidirectional switch controlled by complementary signals on the gates. When the control input is high, both transistors are off and the TG acts as a high impedance state. When the control input is low, one transistor is on providing a conduction path from input to output. The document further analyzes the DC characteristics of a TG under different bias conditions.
The document discusses pass transistor logic circuits. It introduces nMOS pass transistors and their transmission properties. Transmission gates are described as using an nMOS and PMOS pass transistor together to pass both strong 0s and 1s. Transmission gate applications covered include multiplexers, XOR gates, D latches, and D flip-flops. Clock skew management in pass transistor logic is also discussed. Finally, different pass transistor logic families are presented.
The document discusses pass transistor logic circuits. It describes how nMOS pass transistors can transfer logic 1 and 0 signals. Transmission gates are introduced which use both nMOS and pMOS pass transistors to pass strong signals in both directions. Applications of transmission gates include multiplexers, XOR gates, D latches, and D flip-flops. Clock skew management and different pass transistor logic families are also covered.
This document compares the use of complementary pass-transistor logic (CPL) to conventional CMOS design. CPL uses fewer transistors than CMOS gates, has smaller capacitances, and is faster. A 2:1 multiplexer is designed using both CMOS and CPL in Microwind and DSCH2 layout tools. Simulation results show the CPL multiplexer has lower power consumption, smaller area, faster rise/fall delays compared to the CMOS multiplexer. Therefore, CPL offers advantages over conventional CMOS in terms of speed, area, and power-delay products.