Kaushik_Sinha_Resume_Updated_1
- 1. Kaushik Sinha sinha.kaushik20@tamu.edu | 979-985-9080 www.linkedin.com/in/sinhakaushik20 OBJECTIVE: Seeking entry level full time opportunities as a Digital Design Engineer to utilize my skills in hardware design and development. EDUCATION: TEXAS A&M UNIVERSITY, College Station, Texas Aug, 2013 Dec, 2015 Master of Engineering, Electrical Engineering, CGPA 3.78 WEST BENGAL UNIVERSITY OF TECHNOLOGY, West Bengal, India Aug, 2008 Jun, 2012 Bachelor of Technology, Electronics and Instrumentation Engineering, CGPA 4.0 RELEVANT COURSEWORK: Digital Integrated Circuit Design Microprocessor System Design Co-Design of Embedded Systems Microelectronics Device Design Introduction to IC Design and Verification Optimization and Verification of Embedded Systems Low Noise Electronic Design TECHNICAL SKILLS: Tools: Cadence Virtuoso, VCS, Spyglass Design Vision, Prime Time, Verdi SoC Encounter, DC ModelSim, Fizzim Carbon Model Studios Xilinx Platform Studio (XPS) Xilinx Integrated Software Environment: ISE 14 SCADA, LEDIT, MATLAB Hardware Description Language: Verilog, System Verilog Languages: Perl, MxScript (Scripting Language, Carbon Design Studios), C. MLP Intel 85, 86, 55 RSL Logix 500 WORK EXPERIENCE: Samsung Research America, APL-GPU-PEQ Team, Design Intern, Austin, TX May-Dec 2015 RTL Implementation of multiple Floating point instructions using System Verilog for data path units of Samsungs next generation GPUs. Debugged implemented design to resolve bugs and pin point corner case checker mismatch issues. Debugging and Testing- responsible for testing various Data Path units and assisting team in debugging RTL modules. Optimizing implemented RTL design to reduce combinatorial and sequential area, critical path length, and negative slack to reduce power overhead and area of Data Path unit. Compilation & Synthesis Supporting cross site team for post synthesis data analysis, report generation, documenting test environment requirements and product life cycle goals for L0.1 and L0.5 revisions for several blocks in the shader core. Developed automated solution for post synthesis data mining and report generation for PEQ modules using Perl scripts. Accenture India Pvt. Ltd., Associate Systems Engineer, Product Development Jan-Aug 2012 Developed Database Management Solutions for customer support for principal clients. PROJECTS: Texas A&M University, Department of Electrical and Computer Engineering Embedded System Design, Disease Monitoring System, Mentor- Dr. Jiang Hu Jan-May 2015 Implementing an Embedded System Design for Contagious Disease Monitoring in Human Contact Network. Designed proximity sensor based data acquisition system which interact with other users in a controlled environment to track the spread of contagious disease using Probabilistic Models. SoC Design, Hardware Accelerator for Big Data Analytics, Mentor- Dr. Rabi N Mahapatra Sep-Dec 2014 Designed an ASIC for Partitioning Data using range partitioning. Integrated ASIC into A9 Cortex System to create a SoC, Automated the Partitioning process through Shell Script written using MxScript. Compared Single Cored SoC Hardware Performance with Single Threaded Software Partitioner to validate Higher Performance at Lower Cost for Designed SoC vs Software. Microprocessor System Design, Mentor- Dr. Sunil Khatri Sep-Dec 2014 Implemented an IR Remote Controlled Linux based Audio Player in Xilinx XUP Virtex 5 FPGA. Developed a custom IR Decoder peripheral. Designed a Microprocessor Based System using Microblaze and IP Cores. Designed Device Driver Module for IR and Remote Peripherals which were integrated in Linux Kernel. Developed a Linux application that plays directory of Wav for formatted audio files. JPEG Decoder, RTL Design, Mentor- Dr. Jiang Hu May-Aug 2014 Designed the Multiprocessor Architecture of a JPEG Image Decoder on a Behavioral Level. Synthesized the Design using Design Vision to generate the RTL for the ASIC. Automobile Cruise Controller, Mentor- Dr. Gwan Choi Jan-Apr 2014 Designed an Automobile Cruise Controller on a behavioral level and verified its functionality. Synthesized the codes using Design Compiler to generate Gate Level Netlist. Simulated design through standalone test benches. Performed Place and Route on Netlist using SoC Encounter. Improved the delay along critical paths using Static Timing Analysis. H-Tree Clocked Pipelined Adder, Mentor- Dr. Gwan Choi Jan-Apr 2014 Designed and verified an 8 bit Pipelined Adder with buffered H-Tree Clocking at logical level. Designed the Custom Layout of the Gates (Standard Cells) used in design. Performed Standard Cell Characterization of the cells using Transistor Level Implementation on Spectre. Optimized the circuit in terms of Transistor Size, Circuit Area, Delay and Power Consumed. WORK AUTHORIZATION: F1 Visa Authorized to work Full Time after graduation.