Kaushik_Sinha_Resume_Updated_1
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This resume is for Kaushik Sinha, seeking a position as a Digital Design Engineer. He has a Master's degree in Electrical Engineering from Texas A&M University and a Bachelor's degree in Electronics and Instrumentation Engineering from West Bengal University of Technology. His experience includes internships at Samsung Research America working on GPU design and at Accenture India developing database solutions. He is proficient in Verilog, SystemVerilog, and Cadence and Xilinx design tools. His projects include designing an embedded disease monitoring system, hardware accelerator for big data analytics, and FPGA-based audio player.
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This document is a resume for Muhammad Umair Zafar summarizing his qualifications and experience. It outlines his educational background including a MASc from Ryerson University where he is studying measuring energy efficiency between FPGAs and processors. It also details his 1 year of work experience as a hardware design engineer developing boards for FPGAs and CPLDs and lists his relevant skills in software design, hardware design, and communication protocols. His projects include work with parallel computing, FPGA design, and image/audio compression.Fulltime_Resume
Fulltime_ResumePavan Anand Vivekananda
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Pavan Anand Vivekananda is seeking a full-time opportunity in VLSI industry utilizing his experience in ASIC design and verification. He has a Master's degree in Electrical Engineering from University of Minnesota expected in December 2015 and a Bachelor's degree in Electronics and Communication Engineering from R.V. College of Engineering, Bangalore, India. His skills include SystemVerilog, Verilog, UVM, coverage-driven verification, and EDA tools like ModelSim and Incisive. His work experience includes projects developing verification environments for asynchronous FIFOs, eMMC4.5, and UFS at Samsung Research India and measuring SOC design performance at Freescale Semiconductors. His graduate projects includeResume
Resumepraveen.m
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The document provides a resume for Praveen Mehrotra. It summarizes his objective of seeking a full-time position in VLSI circuit design, education including a Master's in electrical engineering and Bachelor's in electronics and communications engineering, and professional experience including design engineering and internship roles. It also lists his skills in HDLs, software languages, and VLSI design tools and provides details of projects implemented during his education.amresh_updated_exp
amresh_updated_expamresh0510
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Amresh Kumar Singh has over 5 years of experience as an Embedded System Engineer. He has a B.Tech in ECE and a postgraduate diploma in embedded system design. His skills include C programming, data structures, operating systems, RTOS, device drivers, Linux, and networking concepts. He has experience working with microcontrollers, BeagleBone, Arduino, and Raspberry Pi. He has completed projects in vehicle-to-vehicle communication using BeagleBone and a password-based home security system using a microcontroller._SOMANATH_
_SOMANATH_Somanath Rudrakshala
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This document contains the resume of Somanath R. Rudrakshala seeking opportunities in embedded system programming and software/device driver development. It summarizes his educational qualifications including a PGDM in Embedded System Design and B.E. in Electronics. It also outlines his over 2 years of work experience in software development roles and lists his technical skills and expertise in areas like embedded C programming, Linux system programming, microcontroller design, and PCB design. It provides details of his past projects, academic qualifications, and additional accolades.Resume
Resumegaurang_narvekar
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This document is a resume for Gaurang Prabhakar Narvekar seeking an internship or full-time position in digital/analog/RF circuit design. He has a MS in Electrical and Computer Engineering from Georgia Tech and a BE in Electronics Engineering from Mumbai University. His relevant experience includes projects in DFE design, SRAM design, wireless transceiver design, and IC fabrication. He also has work experience as a software engineer at Accenture.Resume
Resumegaurang_narvekar
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This document is a resume for Gaurang Prabhakar Narvekar seeking an internship or full-time position in digital/analog/RF circuit design. He has a MS in Electrical and Computer Engineering from Georgia Tech and a BE in Electronics Engineering from Mumbai University. His relevant experience includes projects in DFE design, SRAM design, wireless transceiver design, and IC fabrication. He also has work experience as a software engineer at Accenture.Resume- Akshit Jain
Resume- Akshit JainAkshit Jain
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Akshit Jain is seeking a full-time opportunity in RTL/IC/Hardware Design, ASIC, SoC or Verification with over 2 years of relevant experience. He has a Master's degree in Electrical Engineering from the University of Bridgeport and a Bachelor's degree from Manipal Institute of Technology. His technical skills include languages like Java, Python, C, C++ and hardware design tools. He has internship experience with companies like Elidah Med, Freescale Semiconductor and Defence Research and Development Organization. His academic projects include SRAM design, Android controlled robot and low power VLSI design.Srayan guhathakurta resume
Srayan guhathakurta resumeSrayan Guhathakurta
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Srayan Guhathakurta is a graduate student in telecommunications engineering at UT Dallas with over 4 years of experience as a software engineer. He is currently interning at Microsoft working on Xpert, a tool for monitoring performance metrics in data centers. Previously, he worked at Mahindra Satyam on projects for clients like KPN Telecom and SAAB involving network configuration, capacity management, and application development. He is also working on projects involving a load balancer using SDN, managing smart home appliances via SNMP, and a battery-saving GPS application.Rajas mhaskar resume2k19
Rajas mhaskar resume2k19Rajas Mhaskar
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Rajas Mhaskar has a Master's in Computer Science from UCLA and a Bachelor's/Master's in Engineering from IIT Kharagpur. He has over 3 years of experience in DSP architecture and optimization at Cadence Design Systems. His work involved developing vision software, optimizing neural networks, and analyzing DSP cores for performance and power. While in school, he conducted research in fault detection for analog circuits and accelerated graph networks on CPUs and GPUs. He is proficient in C/C++, Java, Python and parallel frameworks like CUDA and OpenMP.Akash Jinandra EE CPE Resume 7-28-2016
Akash Jinandra EE CPE Resume 7-28-2016Akash Jinandra
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Akash Jinandra has experience in electrical engineering and computer engineering through internships at Hewlett Packard, Texas Instruments, and Advanced Micro Devices. He has skills in programming languages like C, Java, Python and systems like Linux and Windows. Through internships and projects, he has experience with hardware including microcontrollers, FPGAs, and PCB design. He also has leadership experience as chair of the IEEE student chapter at UCF, organizing meetings and projects for over 100 students.updated
updatedAnil Dogra
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Anil Kumar is seeking a position that utilizes his technical expertise and offers learning opportunities. He has years of experience in embedded software and hardware design, including expertise in microcontrollers, programming languages like C and Assembly, and protocols like SPI, UART, I2C, and Bluetooth. His experience includes roles as a team lead, research engineer, and associate consultant where he designed and implemented various embedded systems and products. He has a Bachelor's degree in Electronics and Communication and relevant skills including PCB design, embedded Linux, and wireless modules like GSM and GPS.Kaushik_Sinha_Resume_Updated_1
- 1. Kaushik Sinha sinha.kaushik20@tamu.edu | 979-985-9080 www.linkedin.com/in/sinhakaushik20 OBJECTIVE: Seeking entry level full time opportunities as a Digital Design Engineer to utilize my skills in hardware design and development. EDUCATION: TEXAS A&M UNIVERSITY, College Station, Texas Aug, 2013 – Dec, 2015 Master of Engineering, Electrical Engineering, CGPA – 3.78 WEST BENGAL UNIVERSITY OF TECHNOLOGY, West Bengal, India Aug, 2008 – Jun, 2012 Bachelor of Technology, Electronics and Instrumentation Engineering, CGPA – 4.0 RELEVANT COURSEWORK: ï‚· Digital Integrated Circuit Design ï‚· Microprocessor System Design ï‚· Co-Design of Embedded Systems ï‚· Microelectronics Device Design ï‚· Introduction to IC Design and Verification ï‚· Optimization and Verification of Embedded Systems ï‚· Low Noise Electronic Design TECHNICAL SKILLS: Tools: ï‚· Cadence Virtuoso, VCS, Spyglass ï‚· Design Vision, Prime Time, Verdi ï‚· SoC Encounter, DC ï‚· ModelSim, Fizzim ï‚· Carbon Model Studios ï‚· Xilinx Platform Studio (XPS) ï‚· Xilinx Integrated Software Environment: ISE 14 ï‚· SCADA, LEDIT, MATLAB Hardware Description Language: ï‚· Verilog, System Verilog Languages: ï‚· Perl, MxScript (Scripting Language, Carbon Design Studios), C. ï‚· MLP Intel ’85, ’86, ’55 ï‚· RSL Logix 500 WORK EXPERIENCE: Samsung Research America, APL-GPU-PEQ Team, Design Intern, Austin, TX May-Dec 2015 ï‚· RTL Implementation of multiple Floating point instructions using System Verilog for data path units of Samsung’s next generation GPUs. Debugged implemented design to resolve bugs and pin point corner case checker mismatch issues. ï‚· Debugging and Testing- responsible for testing various Data Path units and assisting team in debugging RTL modules. ï‚· Optimizing implemented RTL design to reduce combinatorial and sequential area, critical path length, and negative slack to reduce power overhead and area of Data Path unit. ï‚· Compilation & Synthesis – Supporting cross site team for post synthesis data analysis, report generation, documenting test environment requirements and product life cycle goals for L0.1 and L0.5 revisions for several blocks in the shader core. ï‚· Developed automated solution for post synthesis data mining and report generation for PEQ modules using Perl scripts. Accenture India Pvt. Ltd., Associate Systems Engineer, Product Development Jan-Aug 2012 ï‚· Developed Database Management Solutions for customer support for principal clients. PROJECTS: Texas A&M University, Department of Electrical and Computer Engineering Embedded System Design, Disease Monitoring System, Mentor- Dr. Jiang Hu Jan-May 2015 ï‚· Implementing an Embedded System Design for Contagious Disease Monitoring in Human Contact Network. ï‚· Designed proximity sensor based data acquisition system which interact with other users in a controlled environment to track the spread of contagious disease using Probabilistic Models. SoC Design, Hardware Accelerator for Big Data Analytics, Mentor- Dr. Rabi N Mahapatra Sep-Dec 2014 ï‚· Designed an ASIC for Partitioning Data using range partitioning. Integrated ASIC into A9 Cortex System to create a SoC, Automated the Partitioning process through Shell Script written using MxScript. ï‚· Compared Single Cored SoC Hardware Performance with Single Threaded Software Partitioner to validate ‘Higher Performance at Lower Cost’ for Designed SoC vs Software. Microprocessor System Design, Mentor- Dr. Sunil Khatri Sep-Dec 2014 ï‚· Implemented an IR Remote Controlled Linux based Audio Player in Xilinx XUP Virtex 5 FPGA. Developed a custom IR Decoder peripheral. Designed a Microprocessor Based System using Microblaze and IP Cores. ï‚· Designed Device Driver Module for IR and Remote Peripherals which were integrated in Linux Kernel. Developed a Linux application that plays directory of Wav for formatted audio files. JPEG Decoder, RTL Design, Mentor- Dr. Jiang Hu May-Aug 2014 ï‚· Designed the Multiprocessor Architecture of a JPEG Image Decoder on a Behavioral Level. ï‚· Synthesized the Design using ‘Design Vision’ to generate the RTL for the ASIC. Automobile Cruise Controller, Mentor- Dr. Gwan Choi Jan-Apr 2014 ï‚· Designed an Automobile Cruise Controller on a behavioral level and verified its functionality. Synthesized the codes using Design Compiler to generate Gate Level Netlist. Simulated design through standalone test benches. ï‚· Performed Place and Route on Netlist using SoC Encounter. Improved the delay along critical paths using Static Timing Analysis. H-Tree Clocked Pipelined Adder, Mentor- Dr. Gwan Choi Jan-Apr 2014 ï‚· Designed and verified an 8 bit Pipelined Adder with buffered H-Tree Clocking at logical level. Designed the Custom Layout of the Gates (Standard Cells) used in design. ï‚· Performed Standard Cell Characterization of the cells using Transistor Level Implementation on Spectre. Optimized the circuit in terms of Transistor Size, Circuit Area, Delay and Power Consumed. WORK AUTHORIZATION: F1 Visaïƒ Authorized to work Full Time after graduation.