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MANOJ_H_RAO_Resume
- 1. Page 1 of 2 MANOJ H RAO CONTACT INFORMATION Address: 915 E 41ST ST APT 209 AUSTIN TX 78751 Ph.: 512-998-9603 Email: manojhrao@utexas.edu EDUCATION University of Texas at Austin Master of Science, Electrical and Computer Engineering (Aug 2013 May 2015) GPA: 3.88/4.00 Relevant Courses: VLSI-1, Computer Architecture, VLSI-2, RF IC Design, Analog IC Design, Algorithms, High Speed Computer Arithmetic, Comp Arch: Parallelism and Locality National Institute of Technology Karnataka Surathkal, India Bachelor of Technology, Electronics and Communication Engineering (July 2007 May 2011) CGPA: 9.32 on a scale of 10 Class Position: 3 in a class of 68 Haute Ecole dIngenerie et de Gestion du Canton de Vaud (HEIG-VD), Switzerland Summer School Participant, July 2010 Scored an aggregate of 93% and earned 4 European credits in Summer University 2010 jointly organised by institutions from India, Switzerland and USA. Courses: Multi-core and concurrent Programming, Machine Intelligence, Eco-Computing, Spatial Localisation and identification of Object based on video Streams, Linear and Non-Linear Approaches to Image Processing PROFESSIONAL EXPERIENCE Texas Instruments India, Bengaluru Design Engineer (Digital Design), High Performance Analog Division (June 2011 July 2013) Digital Filter design, Logic design and Physical design of the digital block(100k gates) of Delta Sigma ADC in 90nm process o Designed a 3-stage Low pass FIR decimation filter at sampling speed of 1.25 GSPS for a Delta-Sigma ADC. o Implemented the designed filter in RTL, defined timing constraints and synthesized and simulated. o Ramped up quickly to learn and implement the flow of physical design (backend) including timing aware PnR(Place and Route), CTS(Clock Tree Synthesis), DRC cleanup and signoff checks using CAD methodology. o Was commended for achieving timing closure and clock tree synthesis for high speed design. Logic Design and Physical Design of Digital block(50k gates) of Pipeline ADC in 180nm process o Designed digital error correction block for 1GHz Pipeline ADC. o Evaluated various data path architectures for power optimisation and latency minimisation. o Using CAD tools did the Physical design in 180nm process, and signoff checks. Designed a flash encoder and dither correction block from RTL to final physical layout in 65 nm process at 1.5 GSPS Designed RTL logic for Timing Generator block, synthesized and simulated Worked on Automatic Test Pattern Generation for various designs Proficient in: o RTL design using VHDL, Verilog and synthesis for data path architectures o Synthesis using Synopsys Design Compiler, Cadence RTL Compiler o Physical design tools: Magma Talus, Cadence SoC Encounter, Timing closure using PrimeTimeSI, Encounter Timing System and signoff checks. NVIDIA, Santa Clara Summer Intern (ASIC), GPU Power (May 2014 August 2014) Functional verification, debugging and testing of Power Management Unit of GPU. Modified a smaller unit to accommodate new features introduced and added tests to verify the new features introduced. PUBLICATION Shrikant Kulkarni, Manoj Rao, Sumam David, Madumbu Venugopala, Senthil Kumar, Robust Hand Gesture Recognition System Using Motion Templates", Proc. International Conference on ITS Telecommunications, St. Petersberg, 2011
- 2. Page 2 of 2 PROJECTS GRADUATE SCHOOL PROJECTS Comparision of different 16-bit floating point division architectures by implementing in layout; as part of VLSI-1 course Design of a front-end low-noise amplifier and baseband quadrature mixer; as part of RFIC course The front end LNA was implemented using common gate topology and the quadrature mixer was implemented using double balanced current steering active mode mixer. Top down design of an embedded SOC with area, timing and power constraints; as part of VLSI-2 course The project goal was to produce a layout from a given RTL and meeting timing, area and power constraints using 28nm CMOS. The steps included synthesis, clock tree generation, placement and routing and the tools used were Synopsys Design Compiler and Synopsys IC Compiler. Comparision of different adder architectures for 8, 16 and 32-bit adders in terms of area, speed and power; as part of High Speed Computer Arithmetic course Design of a differential OTA; as part of Analog IC design course UNDERGRADUATE SCHOOL PROJECTS Optimized Video Analytics on C64x DSP with an application in hand gesture recognition Undergraduate Thesis (June 2010 - April 2011) Guide: Dr.Sumam David S, Dept of ECE, NITK Surathkal Industry mentors: Texas Instruments The basic blocks of video analytics were studied and implemented using Texas Instrument APIs, on a DSP board. The emphasis was on robustness, optimization and processing speed of accumulated optical flow and tracking. A hand gesture recognition system based on Motion Templates, suitable for real-life scenario such as gesture-based power point presentation was developed. Automatic speech recognition using Hidden Markov model On Texas Instruments' TMS320C6713 DSP processor (April 2010 May2010) As part of Digital Signal Processing Lab Course The main objective was to identify speech words, by recognising speech features. This was achieved by extraction of speech features using Mel-frequency wrapping on FFT to obtain spectrum coefficients, which were used to generate Hidden Markov Model with the help of vector quantisation and Baum Welch Algorithm. The recognition was then based on training this model using Viterbi algorithm. SELECT ACADEMIC PROJECTS Real Time Audio Equalizer on Xilinx XC2VP30 FPGA of Virtex XUPV2P board, as part of Digital System Design Lab Course. A multi-band IIR filter was designed with programmability to choose the gain of each band. Musical Fountain Controller: Real time audio signal filtered in frequency by analog circuits. The circuits drive the lights and solenoid valves of fountain according to music played. Design and layout of a 32-bit Barrel shifter on Magic VLSI Layout tool Implementation of speed of key-press detector on ARM 7 based board in assembly language SOFTWARE SKILLS Languages: C, Verilog, VHDL, TCL, Assembly level programming Packages: o MATLAB, Simulink, Pspice, Xilinx ISE, Modelsim o Synopsys Design Compiler, Cadence RTL Compiler, Magma Talus, Cadence SoC Encounter, Synopsys PrimeTime, Synopsys IC Compiler ACTIVITIES AND ACHIEVEMENTS Secured third place in Fox Hunt, an Antenna based treasure hunt in ENGINEER 2009, the annual National Technical Festival of NITK Surathkal Participated in Trade Off, an analog design contest in ENGINEER 2010 Secured second place in Symphony (a musical fountain design contest) in ENGINEER 2010