This document discusses ultra-large scale integration (ULSI) circuits and semiconductor manufacturing processes. It introduces ULSI and its applications. It then summarizes the key steps in the IC fabrication process, including crystal growth, thin film deposition, oxidation, etching, lithography and metallization. Finally, it discusses future trends in ULSI, such as following Moore's Law to continue increasing transistor density, performance and functionality through advances in device physics, materials and technology to shrink dimensions below physical limits.
【Intern Case Study_矽智財】
矽智財 (IP) 是 IC 設計所使用的智慧財產權,是一組事前設計好並驗證完畢、可重複使用的功能組塊,屬於半導體產業的上游,隨著 IC 產業垂直分工化的趨勢而崛起,具有高進入門檻、無庫存、高毛利等特色。
矽智財產業的商業模式為將設計好的 IP 模組授權給買家使用,初次會收取授權金 (License),往後開始量產則轉為收取權利金 (Royalty)。隨著先進製程不斷演進,全球矽智財市場也高速成長,終端市場以消費性電子為大宗,車用與 AI 應用則為主要成長動能。
矽智財在產業鏈、需求面、供給面、相關個股,還有什麼是我們需要注意的呢?一起來看看 Collaborator 的 Intern 們:梁維珉、黃微茹、蔡博獻、謝恩慈、曾筠婷詳盡分析的矽智財產業報告吧!
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Power SiC 2019: Materials, Devices, and Applications by Yole DéveloppementYole Developpement
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This document provides an overview of the types of reports that will be available in 2019 from Yole Développement and its partner companies, System Plus Consulting and KnowMade. A total of over 125 reports will cover 18 technology fields across 6 end markets, including mobile/consumer, automotive, medical, industrial, telecom/infrastructure, and defense/aerospace. The reports will provide market analysis, technology trends, reverse costing analyses, and patent landscape investigations. Custom consulting services are also available to provide more in-depth insights into specific topics.
The semiconductor industry is undergoing dynamic changes as technology challenges escalate due to the end of scaling and declining prices/shortening lifecycles. R&D and manufacturing investment requirements are becoming unaffordable for many smaller companies. As a result, companies globally are adopting an "asset-lite" strategy and manufacturing is moving offshore to large-scale foundries. Revenue growth of the IC industry will remain lower than traditional rates in the single digits rather than double digits, though productivity will still improve at lower rates. Partnerships will be important for development, manufacturing, and delivering technology leadership given mounting investment needs.
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.
More information on that report at https://www.i-micronews.com/advanced-packaging-report/product/p2-5d-3d-tsv-wafer-level-stacking-technology-market-updates-2019.html
1. Unimicron is a leading substrate manufacturer that has expanded its product portfolio over time to include finer line designs and smaller bump pitches, posing new challenges for metrology.
2. 2D AOI is used to detect small "mouse bite" defects not found by electrical tests that could cause reliability issues, but it faces challenges discerning real defects from false alarms or similar features like oxidation.
3. As designs evolve to include finer lines and pitches, equipment vendors are expected to provide higher resolution 3D metrology tools that can directly assess defects without multiple scans to reduce false alarms, while also offering faster throughput and automated defect mapping.
Power SiC 2019: Materials, Devices, and Applications by Yole DéveloppementYole Developpement
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This document provides an overview of the types of reports that will be available in 2019 from Yole Développement and its partner companies, System Plus Consulting and KnowMade. A total of over 125 reports will cover 18 technology fields across 6 end markets, including mobile/consumer, automotive, medical, industrial, telecom/infrastructure, and defense/aerospace. The reports will provide market analysis, technology trends, reverse costing analyses, and patent landscape investigations. Custom consulting services are also available to provide more in-depth insights into specific topics.
The semiconductor industry is undergoing dynamic changes as technology challenges escalate due to the end of scaling and declining prices/shortening lifecycles. R&D and manufacturing investment requirements are becoming unaffordable for many smaller companies. As a result, companies globally are adopting an "asset-lite" strategy and manufacturing is moving offshore to large-scale foundries. Revenue growth of the IC industry will remain lower than traditional rates in the single digits rather than double digits, though productivity will still improve at lower rates. Partnerships will be important for development, manufacturing, and delivering technology leadership given mounting investment needs.
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.
More information on that report at https://www.i-micronews.com/advanced-packaging-report/product/p2-5d-3d-tsv-wafer-level-stacking-technology-market-updates-2019.html
1. Unimicron is a leading substrate manufacturer that has expanded its product portfolio over time to include finer line designs and smaller bump pitches, posing new challenges for metrology.
2. 2D AOI is used to detect small "mouse bite" defects not found by electrical tests that could cause reliability issues, but it faces challenges discerning real defects from false alarms or similar features like oxidation.
3. As designs evolve to include finer lines and pitches, equipment vendors are expected to provide higher resolution 3D metrology tools that can directly assess defects without multiple scans to reduce false alarms, while also offering faster throughput and automated defect mapping.
Comparison of main players AP: Apple A10 with inFO vs. Qualcomm Snapdragon 820 with MCeP packaging technology vs. HiSilicon Kirin 955 & Samsung Exynos 8 with standard Package-on-Package
Five major players are sharing the smartphone application processors (AP) market. Among them, Qualcomm, Apple, Samsung and HiSilicon propose the most powerful AP. They use almost the same technology node for the die, and the innovation is now at the packaging level. During this year, we observed different technologies inside the four main smartphone flagships: classic Package-on-Package (PoP) developed by Amkor for the Kirin 955 and for the Exynos 8, Molded Core Embedded Package (MCeP) technology developed by Shinko for the Snapdragon 820 and integrated Fan-Out packaging (inFO) developed by TSMC for the A10.
Located under the DRAM chip on the main board, the AP are packaged using PoP technology. The Apple A10 can be found in the iPhone 7 series. The HiSilicon Kirin 955 can be found in the Huawei P9 and the Samsung Exynos 8 as the Qualcomm Snapdragon 820 can be found in the Samsung Galaxy S7 series depending on the world version (US and Asia for the Snapdragon and International for the Exynos).
In this report, we highlight the differences and the innovations of the packages chosen by the end-user OEMs. Whereas some AP providers like for HiSilicon or Samsung choose to consider conventional PoP with embedded land-side capacitor (LSC), others like Apple or Qualcomm use innovative technologies like Fan-Out PoP and silicon based Deep Trench LSC or embedded die packaging with advanced PCB substrate. The detailed comparison between the four players will give the pros and the cons of the packaging technologies.
This report also compares the costs of the different approaches and includes a detailed technical comparison between the packaging structure of the Qualcomm Snapdragon 820, the Samsung Exynos 8, the HiSilicon Kirin 955 and the Apple A10.
More information on: http://www.i-micronews.com/reports.html
Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole De...Yole Developpement
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Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?
Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology...
How to Make Awesome 狠狠撸Shares: Tips & Tricks狠狠撸Share
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Turbocharge your online presence with 狠狠撸Share. We provide the best tips and tricks for succeeding on 狠狠撸Share. Get ideas for what to upload, tips for designing your deck and more.
狠狠撸Share is a global platform for sharing presentations, infographics, videos and documents. It has over 18 million pieces of professional content uploaded by experts like Eric Schmidt and Guy Kawasaki. The document provides tips for setting up an account on 狠狠撸Share, uploading content, optimizing it for searchability, and sharing it on social media to build an audience and reputation as a subject matter expert.
1.91 Inch OLED Display Module Resolution 240*536 MIPI Interface for Wearable ...Shawn Lee
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This is a 1.91" AMOLED-Display has 240x536 high resolution with a MIPI interface. It`s designed for wearable devices, in addition, it also can be used in other industries, such as handheld pulse Oximeter in the medical industry, smart home products, etc.
The key technology of this AMOLED-Display is LTPS, Real RGB, Thinning.
Whatsapp: 86 18566294218
Skype: panoxshawn@outlook.com
Email: shawn.lee@panoxdisplay.com
OLED/LCD supplier: www.panoxdisplay.com
8. Fab 10 TSMC Headquarters & Fab 2, 3, 5, 8, 12 Fab 6 & 14 TSMC North America WaferTech TSMC Europe TSMC Japan SSMC TSMC China TSMC India TSMC Korea TSMC Worldwide Operations & Affiliates
14. 參考書單 半導體製造技術 羅文雄 譯 滄海出版社 半導體元件物理與製作技術 施敏 高立出版社 積體電路製程及設備技術手冊 張俊彥 主編 中華民國產業科技發展協進會 Silicon Processing for VLSI Era Volume I Stanley Wolf ISBN 0-9616721-3-7 世界是平的 (The world is flat) 湯馬斯 . 佛里曼 雅言出版 台積 DNA 天下出版