飪� Involved in implementing GLN to GDS convergence for small ASIC.
飪� Well trained in ASIC PD flow involving Design Planning, Floor Plan, Placement and routing, Extraction, Timing Closure and Physical Verification.
飪� Experience in using tools like Synopsys (IC Compiler, PrimeTime), Mentor Graphics (Caliber, IC Studio).
飪� Through knowledge of PD concepts like Liberty, MCMM, OCV, DFT, Blockages, CTS, Core utilization, SDC, TLU+ and Signal Integrity.
飪� Have ability to resolve reliability issues like IR Drop Analysis, Congestion, Cross-talk, EM, Antenna effect , DFM and OPC.
飪� Analytical skills of Pre-layout and Post-layout STA reports.
飪� Basic awareness in scripting languages like PERL and ...
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