Design Engineer (Modelling and Simulation Division) at Sankalp Semiconductor Pvt Ltd
About
- 1 year experience in pre-silicon SOC verification at Intel Technologies.
- Understanding of JTAG and TAP network. Also worked on BSCAN validation with automation using Perl scripting.
- Exposure to tools : Synopsys鈥檚 VCS and DVE, Cadence鈥檚 virtuoso schematic editor.
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