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Introduction to
CMOS VLSI
Design
Lecture 14:
CAMs, ROMs, and PLAs
David Harris
Harvey Mudd College
Spring 2004

CMOS VLSI Design
14: CAMs, ROMs, and PLAs �ݺ�ߣ 2
Outline
 Content-Addressable Memories
 Read-Only Memories
 Programmable Logic Arrays

CMOS VLSI Design
CAMs
 Extension of ordinary memory (e.g. SRAM)
– Read and write memory as usual
– Also match to see which words contain a key
CAM
adr data/key
match
read
write

CMOS VLSI Design
10T CAM Cell
 Add four match transistors to 6T SRAM
– 56 x 43 l unit cell
bit bit_b
word
match
cell
cell_b

CMOS VLSI Design
CAM Cell Operation
 Read and write like ordinary SRAM
 For matching:
– Leave wordline low
– Precharge matchlines
– Place key on bitlines
– Matchlines evaluate
 Miss line
– Pseudo-nMOS NOR of match lines
– Goes high if no words match
row
decoder
weak
miss
match0
match1
match2
match3
clk
column circuitry
CAM cell
address
data
read/write

CMOS VLSI Design
Read-Only Memories
 Read-Only Memories are nonvolatile
– Retain their contents when power is removed
 Mask-programmed ROMs use one transistor per bit
– Presence or absence determines 1 or 0

CMOS VLSI Design
ROM Example
 4-word x 6-bit ROM
– Represented with dot diagram
– Dots indicate 1’s in ROM
Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010
ROM Array
2:4
DEC
A0
A1
Y0
Y1
Y2
Y3
Y4
Y5
weak
pseudo-nMOS
pullups
Looks like 6 4-input pseudo-nMOS NORs

CMOS VLSI Design
ROM Array Layout
 Unit cell is 12 x 8 l (about 1/10 size of SRAM)
Unit
Cell

CMOS VLSI Design
Row Decoders
 ROM row decoders must pitch-match with ROM
– Only a single track per word!

CMOS VLSI Design
Complete ROM Layout

CMOS VLSI Design
PROMs and EPROMs
 Programmable ROMs
– Build array with transistors at every site
– Burn out fuses to disable unwanted transistors
 Electrically Programmable ROMs
– Use floating gate to turn off unwanted transistors
– EPROM, EEPROM, Flash
n+
p
Gate
Source Drain
bulk Si
Thin Gate Oxide
(SiO2)
n+
Polysilicon
Floating Gate

CMOS VLSI Design
Building Logic with ROMs
 Use ROM as lookup table containing truth table
– n inputs, k outputs requires __ words x __ bits
– Changing function is easy – reprogram ROM
 Finite State Machine
– n inputs, k outputs, s bits of state
– Build with ________ bit ROM and ____ bit reg
n
inputs
2
n
wordlines
ROM Array
k outputs
DEC
ROM
inputs outputs
state
n k
s
k
s

CMOS VLSI Design
Building Logic with ROMs
 Use ROM as lookup table containing truth table
– n inputs, k outputs requires 2n words x k bits
– Changing function is easy – reprogram ROM
 Finite State Machine
– n inputs, k outputs, s bits of state
– Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
n
inputs
2
n
wordlines
ROM Array
k outputs
DEC
ROM
inputs outputs
state
n k
s
k
s

CMOS VLSI Design
Example: RoboAnt
Let’s build an Ant
Sensors: Antennae
(L,R) – 1 when in contact
Actuators: Legs
Forward step F
Ten degree turns TL, TR
Goal: make our ant smart enough to
get out of a maze
Strategy: keep right antenna on wall
(RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman)
L R

CMOS VLSI Design
Lost in space
 Action: go forward until we hit something
– Initial state

CMOS VLSI Design
Bonk!!!
 Action: turn left (rotate counterclockwise)
– Until we don’t touch anymore

CMOS VLSI Design
A little to the right
 Action: step forward and turn right a little
– Looking for wall

CMOS VLSI Design
Then a little to the right
 Action: step and turn left a little, until not touching

CMOS VLSI Design
Whoops – a corner!
 Action: step and turn right until hitting next wall

CMOS VLSI Design
Simplification
 Merge equivalent states where possible

CMOS VLSI Design
State Transition Table
S1:0 L R S1:0’ TR TL F
00 0 0 00 0 0 1
00 1 X 01 0 0 1
00 0 1 01 0 0 1
01 1 X 01 0 1 0
01 0 1 01 0 1 0
01 0 0 10 0 1 0
10 X 0 10 1 0 1
10 X 1 11 1 0 1
11 1 X 01 0 1 1
11 0 0 10 0 1 1
11 0 1 11 0 1 1
Lost
RCCW
Wall1
Wall2

CMOS VLSI Design
ROM Implementation
 16-word x 5 bit ROM
ROM
L, R
S1:0
TL, TR, F
S'1:0
S1
' S0
' TR'TL' F'
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4:16
DEC
S1 S0 L R

CMOS VLSI Design
PLAs
 A Programmable Logic Array performs any function
in sum-of-products form.
 Literals: inputs & complements
 Products / Minterms: AND of literals
 Outputs: OR of Minterms
 Example: Full Adder
out
s abc abc abc abc
c ab bc ac
   
  
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c out
c
Minterms
Inputs Outputs

CMOS VLSI Design
NOR-NOR PLAs
 ANDs and ORs are not very efficient in CMOS
 Dynamic or Pseudo-nMOS NORs are very efficient
 Use DeMorgan’s Law to convert to all NORs
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
out
c
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
out
c

CMOS VLSI Design
PLA Schematic & Layout
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
out
c

CMOS VLSI Design
PLAs vs. ROMs
 The OR plane of the PLA is like the ROM array
 The AND plane of the PLA is like the ROM decoder
 PLAs are more flexible than ROMs
– No need to have 2n rows for n inputs
– Only generate the minterms that are needed
– Take advantage of logic simplification

CMOS VLSI Design
Example: RoboAnt PLA
 Convert state transition table to logic equations
S1:0 L R S1:0’ TR TL F
00 0 0 00 0 0 1
00 1 X 01 0 0 1
00 0 1 01 0 0 1
01 1 X 01 0 1 0
01 0 1 01 0 1 0
01 0 0 10 0 1 0
10 X 0 10 1 0 1
10 X 1 11 1 0 1
11 1 X 01 0 1 1
11 0 0 10 0 1 1
11 0 1 11 0 1 1
1 0
0
1 0
TR S S
TL S
F S S


 

CMOS VLSI Design
RoboAnt Dot Diagram
AND Plane OR Plane
1 0
S S
1
LS
0
LRS
R
1
LS
0
S
0
LS
1 '
S
1
S 0
S L
0 '
S TR TL F
R
1
S
0
S
1 0 1 0
1 0
1 0
0
1 0
1'
0'
S S S LS LRS
S R LS LS
TR S S
TL S
F S S
  
  


 

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