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MANSOORALIKHAN A
DOB: 10/06/1993
3/566, Marukkalampatti Village,
Alapuram Post, EMAIL: mansooralikhan2016@gmail.com
Pappireddipatti Taluk, PH. NO: 9087503679
Dharmapuri Dist.
OBJECTIVE
To pursue a challenging career in an organization that offers continuous building of
conventional skills, innovative ingenuity and promotes exposure to the recent technologies.
ACADEMIC DETAILS
COURSE INSTITUTE YEAR PERCENTAGE/
CGPA
M.E
(VLSI Design)
College of Engineering
Guindy(CEG),Anna University 2014-2016 7.20
B.E
(ECE)
Anna University of Technology,
Trichy 2010-2014 7.34
HSC Indian Matriculation Higher
Secondary School
2008-2010 92.9%
SSLC Government Higher Secondary
School
2008 92.4%
TECHNICAL EXPOSURE
Programming Language : C, Verilog HDL
IC Design Tools : Xilinx ISE, Cadence
Simulation Tools : MATLAB, LT Spice
Basic Knowledge : Digital Electronics, Digital System Design, ASIC
RESEARCH AND PROJECTS
ME PROJECT (Current):
Segmentation Based Energy Efficient Approximate
Multiplier for Digital Signal Processing
 The purpose of this project is to design and construct low power, area efficient
multiplier.
 In this proposed multiplier ESSM architecture, the area has reduced compared to
other multiplier architectures which process same number of bits.
 My work is to implement new multiplication technique in Xilinx ISE and Power,
Area, Delay calculated by cadence tool.
BE PROJECT:
A True Random-Based Differential Power Analysis Countermeasure
Circuit for an AES Engine
 The purpose of this project resolving a security problem on ring oscillators and
implementing a new architecture with self-generated true random sequence.
 The true random based architecture is implemented with an AES in Xilinx tool.
AWARDS AND ACHIEVEMENTS
 Journal Publication: My project Segmentation Based Energy Efficient
Approximate Multiplier for Digital Signal Processing  has been published in the
journal IJARECE(The International Journal of Advanced Research in
Electronics and Communication Engineering)
 Attended a training program on Telecommunication in BSNL, Trichy.
 Attended a training program on UNIQ technology at Chennai.
 Participated in the National workshop on BOSS LINUX Operating system
organized by Madras Institute of Technology, Chennai.
 Participated a workshop on the field of Digital Signal Processing in Dhanalakshmi
Srinivasan Engineering College, perambalur.
 Participated in the National workshop on DIGITAL CUSTOM IC DESIGN
USING CADENCE EDA TOOLS in College of Engineering Guindy.
OTHER ACHIEVEMENTS
 Qualified in TANCET-2014 with 43 marks.
 School First in State Board for the memorial of Hon. Ex Chiefminister Mr. Kamarajar
Mudhalvan award.
 School first in Higher Secondary Examination of Tamilnadu State Board.
PERSONAL DETAILS
Date of birth : 10.06.1993
Sex : Male
Nationality : Indian
Marital Status : Single
Languages known : English, Tamil (Read and Write)
Hobbies : Reading and playing cricket
DECLARATION
I hereby declare that all the above details furnished by me are true and correct to the best
of my knowledge and belief.
DATE :
PLACE: CHENNAI ( A. Mansooralikhan)

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Mansooralikhan

  • 1. MANSOORALIKHAN A DOB: 10/06/1993 3/566, Marukkalampatti Village, Alapuram Post, EMAIL: mansooralikhan2016@gmail.com Pappireddipatti Taluk, PH. NO: 9087503679 Dharmapuri Dist. OBJECTIVE To pursue a challenging career in an organization that offers continuous building of conventional skills, innovative ingenuity and promotes exposure to the recent technologies. ACADEMIC DETAILS COURSE INSTITUTE YEAR PERCENTAGE/ CGPA M.E (VLSI Design) College of Engineering Guindy(CEG),Anna University 2014-2016 7.20 B.E (ECE) Anna University of Technology, Trichy 2010-2014 7.34 HSC Indian Matriculation Higher Secondary School 2008-2010 92.9% SSLC Government Higher Secondary School 2008 92.4% TECHNICAL EXPOSURE Programming Language : C, Verilog HDL IC Design Tools : Xilinx ISE, Cadence Simulation Tools : MATLAB, LT Spice Basic Knowledge : Digital Electronics, Digital System Design, ASIC RESEARCH AND PROJECTS ME PROJECT (Current): Segmentation Based Energy Efficient Approximate Multiplier for Digital Signal Processing The purpose of this project is to design and construct low power, area efficient multiplier. In this proposed multiplier ESSM architecture, the area has reduced compared to other multiplier architectures which process same number of bits. My work is to implement new multiplication technique in Xilinx ISE and Power, Area, Delay calculated by cadence tool.
  • 2. BE PROJECT: A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine The purpose of this project resolving a security problem on ring oscillators and implementing a new architecture with self-generated true random sequence. The true random based architecture is implemented with an AES in Xilinx tool. AWARDS AND ACHIEVEMENTS Journal Publication: My project Segmentation Based Energy Efficient Approximate Multiplier for Digital Signal Processing has been published in the journal IJARECE(The International Journal of Advanced Research in Electronics and Communication Engineering) Attended a training program on Telecommunication in BSNL, Trichy. Attended a training program on UNIQ technology at Chennai. Participated in the National workshop on BOSS LINUX Operating system organized by Madras Institute of Technology, Chennai. Participated a workshop on the field of Digital Signal Processing in Dhanalakshmi Srinivasan Engineering College, perambalur. Participated in the National workshop on DIGITAL CUSTOM IC DESIGN USING CADENCE EDA TOOLS in College of Engineering Guindy. OTHER ACHIEVEMENTS Qualified in TANCET-2014 with 43 marks. School First in State Board for the memorial of Hon. Ex Chiefminister Mr. Kamarajar Mudhalvan award. School first in Higher Secondary Examination of Tamilnadu State Board. PERSONAL DETAILS Date of birth : 10.06.1993 Sex : Male Nationality : Indian Marital Status : Single Languages known : English, Tamil (Read and Write) Hobbies : Reading and playing cricket DECLARATION I hereby declare that all the above details furnished by me are true and correct to the best of my knowledge and belief. DATE : PLACE: CHENNAI ( A. Mansooralikhan)