Resume_Jayachandra
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Jayachandra Vudumula is a RTL design engineer with over 3 years of experience developing FPGA and ASIC designs using VHDL and Verilog. He has expertise in developing Ethernet, HDLC, E1 and other networking protocol IP cores. Some of the projects he has worked on include developing a GFP framer, Ethernet MAC, E1 framer, and static router designs for networking equipment. He is looking for a new position where he can further contribute his digital design skills.
Resume_Jayachandra
- 1. Jayachandra Vudumula E-mail: jayachandra.vudumula@gmail.com Mobile: +91-8884445613 Objective: To be a part of organization that provides an atmosphere of mutual growth and benefits, where I can contribute my skills and experience. Career summary: Currently working as an RTL design Engineer in HCL Technologies, Bangalore. Over all experience of 3.5 years in VLSI Front-end design. Working as an R&D Engineer in NOMUS COMM SYSTEMS, Hyderabad from 2013 to 2016 Experience in developing block level design and Integration of IPs using Verilog, VHDL and system Verilog. Expertise in developing Ethernet MAC (RMII, SMII, MII). Expertise in developing L2 layer IP blocks for network protocols like GFP, HDLC, E1, Ethernet (MAC), PDH, SDH networks. Expertise in developing SRAM, SPI, UART and interface protocols. Experience of real time debugging using Techtronics digital oscilloscope and JTAG Debug tools in Quartus. FPGA design flow from RTL design to Altera Quartus tool flow. Knowledge on AMBA AHB & AMBA APB and SDR SDRAM. Knowledge on TCP/IP OSI layer protocols. Core Skills: Languages : VHDL, Verilog HDL, system Verilog and C. Simulators : modelsim FPGA Tools : Altera - Quartus II IDE. FPGA devices : Altera - Cyclone IV E family Protocols : Ethernet RMII, SMII, MII, SPI, UART and AMBA. Ethernet Testing tool : Wire shark. Testing : Experience with JTAG logic analyzers, Techtronics Oscilloscope. Operating systems : Linux, windows xp, windows 7. Scripting : UNIX & SHELL scripting. Educational summary: MSc Electronics & Communications in Sri Krishna Devaraya University, Anantapur with 79%. BSc Electronics in Sreenivasa Degree College, Dharmavaram with 83%. Intermediate in Govt. junior college, Dharmavaram with 83%. SSC in SPCS municipal high school, Dharmavaram with 83%.
- 2. IP's Developed: 1. Name : GFP (Generic Framing Procedure) Role : RTL design engineer Description : It is a multiplexing procedure as per ITU-T G.7041. Mapping variable is length Client signals over TDM signals. Here GFP-F framing procedure developed and Mapping Ethernet packets of different lengths into GFP frames. Design blocks : GFP-F TX-framer, Rx-framer CRC-32, CRC-16 generator Scrambler, descrambler. 2. Name : Ethernet MAC using DMA controlling process. Role : RTL design engineer Description : Developed as per IEEE 802.3 and IEEE 802.1Q standards in MII, RMII and SMII modes. In this receiving and validating each Ethernet packet based on Hardware address, IP address, type of packet and CRC check sum calculation. If the receiving packet satisfy all these conditions then the packet is sending to processor using circular buffer descriptors concept. Design blocks : Ethernet Rx, Ethernet TX CRC Generator and checker Interrupt Generation Projects: 1. Name : NOMUS Gateway e E1/V.35 Company : Nomus Comm Systems Duration : oct_2013 to Feb-2014 Role : RTL design engineer Tools & HDL : Altera Quartus 10.0, Modelsim, NIOS II & VHDL IP's included : E1-Framer, Digital PLL Description : This project is about Plesio-synchronous Digital Hierarchy (PDH) as per ITU-T G.703 standard, transmit the data long distance through SHDSL. Data is checking and validating by CRC-4 polynomial. This product is working in two modes, 1. E1 mode 2. V35 mode E1 is always working on 2 Mbps and V.35 interface supports Nx64 data rates. Nx64 clocks are generated by digital PLL. This project supports maximum of 2Mbps on 2-wire and 4 Mbps on 4-wire channels. Design blocks : E1- Framer, E1_Deframer CRC-4 Generator & Checker Digital PLL.
- 3. 2. Name : NOMUS Gwe-ES (Ver1 & Ver2) Company : Nomus Comm Systems Role : RTL design engineer Tools & HDL : Altera Quartus 10.0, Modelsim, NIOS II & VHDL Duration : May-2014 to March- 2015 IP's included : VCAT-LCAS, GFP Description : This project is about transmission of Ethernet data over 2 DSL (Digital Subscriber Line) lines. Ethernet data is mapped into GFP-F and distributed between 2 DSL lines using VCAT-LCAS protocol. Design blocks : Data mapper & de-mapper according to time slot configuration. Data multiplexing logic's. SRAM Controller. 3. Name : NOMUS GW e RB Static Router Company : Nomus Comm Systems Duration : July-2015 to APRL-2016 Role : RTL design engineer Tools & HDL : Altera Quartus 10.0, Modelsim, NIOS II & VHDL, Verilog IPs included : HDLC, ETHERNET MAC and Maintaining MAC and IP tables. Description : This project about routing of Ethernet packets on different networks. This product is working on two modes namely, 1. Router 2. Bridge Ethernet packets are mapped into HDLC and transmitting through SHDSL and de-mapping the packets, packet validation and ERROR detection is performing with CRC-16 through the IPv4 header. Routing process done by maintaining static routing table and Dynamic MAC tables. Key blocks : CRC-16 calculation and insertion for IPv4 header Error detection, packet validation Transmitting data through HDLC blocks. Personal details: Date of birth : 16th march 1991 Nationality : Indian Marital Status : single Address : Venkateswara layout, Madiwala, BTM 1st stage, Bangalore 560068. - Jayachandra vudumula