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Government Engineering
college,Bhavnagar
semester: 3
Branch: Computer (2015)
Name:- Paresh Parmar
subject: Digital Electronics
Enrollment No: 140210107040
Topic: Sequential Circuits

Combinational Logic
 Combinational Logic:
 Output depends only on current input
 Has no memory
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Sequential Logic
 Sequential Logic:
 Output depends not only on current input but also on
past input values, e.g., design a counter
 Need some type of memory to remember the past input
values
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Sequential Circuits
2016/11/8 Sequential Circuits 44
Circuits that we
have learned
so far
Information Storing
Circuits
Timed “States”

Sequential Logic: Concept
 Sequential Logic circuits remember past inputs and
past circuit state.
 Outputs from the system are
“fed back” as new inputs
 With gate delay and wire delay
 The storage elements are circuits that are capable of
storing binary information: memory.
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Synchronous vs. Asynchronous
There are two types of sequential circuits:
 Synchronous sequential circuit: circuit output
changes only at some discrete instants of time.
This type of circuits achieves synchronization by
using a timing signal called the clock.
 Asynchronous sequential circuit: circuit output
can change at any time (clockless).
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Clock Period
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FF FFCombinational
Circuit
Smallest clock period = largest combinational
circuit delay between any two directly connected
FF, subjected to impact of FF setup time.
FF

SR Latch (NAND version)
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S’
R’
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’0
0
1
1
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
0 1 Hold
1 0 Set
0 1 Reset
1 0 Hold
1 1 Disallowed

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SR Latch with Clock signal
Latch is sensitive to input changes ONLY when C=1

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D Latch with Transmission Gates
 C=1 TG1 closes and TG2 opens Q’=D’ and Q=D
 C=0 TG1 opens and TG2 closes Hold Q and Q’
2
1

Flip-Flops
 Latches are “transparent” (= any change on the inputs
is seen at the outputs immediately when C=1).
 This causes synchronization problems.
 Solution: use latches to create flip-flops that can
respond (update) only on specific times (instead of
any time).
 Types: RS flip-flop and D flip-flop
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S R CLK Q Q’
0 0 1 Q0 Q0’ Store
0 1 1 0 1 Reset
1 0 1 1 0 Set
1 1 1 1 1 Disallowed
X X 0 Q0 Q0’ Store
Master-Slave FF configuration
using SR latches (cont.)
•When C=1, master is enabled and
stores new data, slave stores old
data.
•When C=0, master’s state passes
to enabled slave, master not
sensitive to new data (disabled).

Characteristic Tables
 Defines the logical properties of a flip-flop (such as a
truth table does for a logic gate).
 Q(t) – present state at time t
 Q(t+1) – next state at time t+1
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Characteristic Tables (cont.)
SR Flip-Flop
S R Q(t+1) Operation
0 0 Q(t) No change/Hold
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined/Invalid
2016/11/8 1414

Sequential Circuit Analysis
 Analysis: Consists of obtaining a suitable description that
demonstrates the time sequence of inputs, outputs, and
states.
 Logic diagram: Boolean gates, flip-flops (of any kind), and
appropriate interconnections.
 The logic diagram is derived from any of the following:
 Boolean Equations (FF-Inputs, Outputs)
 State Table
 State Diagram
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Example (continued)
 Boolean equations for the
functions:
 A(t+1) = A(t)x(t) +
B(t)x(t)
 B(t+1) = A’(t)x(t)
 y(t) = x’(t)(B(t) + A(t))
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C
D Q
Q
C
D Q
Q'
y
x
A
A’
B
CP
Next State
Output

State Table Characteristics
 State table – a multiple variable table with the following
four sections:
 Present State – the values of the state variables for each allowed
state.
 Input – the input combinations allowed.
 Next-state – the value of the state at time (t+1) based on the
present state and the input.
 Output – the value of the output as a function of the present
state and (sometimes) the input.
 From the viewpoint of a truth table:
 the inputs are Input, Present State
 and the outputs are Output, Next State
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Example: State Table
 The state table can be filled in using the next state and output
equations:
 A(t+1) = A(t)x(t) + B(t)x(t)
 B(t+1) = A (t)x(t);
 y(t) = x (t)(B(t) + A(t))
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Present State Input Next State Output
A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

State Diagrams
 The sequential circuit function can be represented in
graphical form as a state diagram with the following
components:
 A circle with the state name in it for each state
 A directed arc from the Present State to the Next State for each state
transition
 A label on each directed arc with the Input values which causes the
state transition, and
 A label:
 On each circle with the output value produced, or
 On each directed arc with the output value produced.
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Example: State Diagram
 Diagram gets
confusing for
large circuits
 For small circuits,
usually easier to
understand than
the state table
2016/11/8 2020
A B
0 0
0 1 1 1
1 0
x=0/y=1 x=1/y=0
x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0

Summary
 Sequential circuit timing analysis
 Flip-Flop
 Transmission gate based flip-flop design
 Setup time
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Sequential circuits

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