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CS1104-13 Lecture 13: Sequential Logic:
Counters and Registers
1
Sequential Logic
Counters
 Introduction: Counters
 Asynchronous (Ripple) Counters
 Synchronous (Parallel) Counters

CS1104-13 Lecture 13: Sequential Logic:
2
Sequential Logic
Registers
 Introduction: Registers
 Simple Registers
 Registers with Parallel Load
 Using Registers to implement Sequential Circuits
 Shift Registers
 Serial In/Serial Out Shift Registers
 Serial In/Parallel Out Shift Registers
 Parallel In/Serial Out Shift Registers
 Parallel In/Parallel Out Shift Registers

CS1104-13 Introduction: Counters 3
Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
 synchronous (parallel) counters
 asynchronous (ripple) counters
 Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.

CS1104-13 Asynchronous (Ripple) Counters 6
Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
 Also known as ripple counters, as the input clock
pulse “ripples” through the counter – cumulative
delay is a drawback.
 n flip-flops  a MOD (modulus) 2n
counter. (Note: A
MOD-x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input
clock frequency by the MOD number of the counter,
hence a counter is also a frequency divider.

 Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock input
of the next more-significant flip-flop.
K
J
K
J
HIGH
Q0 Q1
Q0
FF1
FF0
CLK C
C
Timing diagram
00  01  10  11  00 ...
4
3
2
1
CLK
Q0
Q0
Q1
1 1
1 1
0
0 0
0 0
0

 Example: 3-bit ripple binary counter.
K
J
K
J
Q0 Q1
Q0
FF1
FF0
C
C
K
J
Q1
C
FF2
Q2
CLK
HIGH
4
3
2
1
CLK
Q0
Q1
1 1
1 1
0
0 0
0 0
0
8
7
6
5
1 1
0 0
1 1
0 0
Q2 0 0
0 0 1 1 1
1 0
Recycles back to 0

 Example: 4-bit ripple binary counter (negative-edge
triggered).
K
J
K
J
Q1
Q0
FF1
FF0
C
C
K
J
C
FF2
Q2
CLK
HIGH
K
J
C
FF3
Q3
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0
Q1
Q2
Q3

CS1104-13 Synchronous (Parallel) Counters 10
Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
 We can design these counters using the sequential
logic design process.

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