This document describes the system startup process for Cortex-M series processors. Upon reset, the processor will fetch the main stack pointer (MSP) and reset handler address from the vector table located at address 0x0. The reset handler will then execute in privileged thread mode. Interrupts are initially disabled. The MPU is also disabled initially, allowing access to all memory regions. The document then discusses setting up the vector table and performing additional initialization steps like MPU configuration in the reset handler.
AAME ARM Techcon2013 004v02 Debug and OptimizationAnh Dung NGUYEN
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This document discusses software debug and optimization techniques for ARM Cortex-M microcontrollers. It covers the following key points in 3 sentences:
The document discusses various debug tools and components used for ARM Cortex-M microcontrollers, including the Keil MDK development suite, debug hardware interfaces, and the Flash Patch and Breakpoint, Data Watchpoint and Trace, and Instrumentation Trace Macrocell components. It also covers compiler configuration and optimization techniques in ARM's compiler such as setting the optimization level and architecture, using volatile variables properly, and enabling instruction scheduling. The document provides an overview of debug modes, breakpoints, and trace features supported by the Cortex-M architecture as well as the various physical debug interfaces that can
This document describes the system startup process for Cortex-M series processors. Upon reset, the processor will fetch the main stack pointer (MSP) and reset handler address from the vector table located at address 0x0. The reset handler will then execute in privileged thread mode. Interrupts are initially disabled. The MPU is also disabled initially, allowing access to all memory regions. The document then discusses setting up the vector table and performing additional initialization steps like MPU configuration in the reset handler.
AAME ARM Techcon2013 004v02 Debug and OptimizationAnh Dung NGUYEN
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This document discusses software debug and optimization techniques for ARM Cortex-M microcontrollers. It covers the following key points in 3 sentences:
The document discusses various debug tools and components used for ARM Cortex-M microcontrollers, including the Keil MDK development suite, debug hardware interfaces, and the Flash Patch and Breakpoint, Data Watchpoint and Trace, and Instrumentation Trace Macrocell components. It also covers compiler configuration and optimization techniques in ARM's compiler such as setting the optimization level and architecture, using volatile variables properly, and enabling instruction scheduling. The document provides an overview of debug modes, breakpoints, and trace features supported by the Cortex-M architecture as well as the various physical debug interfaces that can
The document discusses ARM's new Accredited ARM Engineer (AAE) program, which aims to establish an industry-wide standard for accrediting engineers with ARM-related knowledge through computer-based exams. It notes that computing is increasingly mobile and powered by ARM technology, creating demand for well-qualified ARM engineers. The AAE exams cover ARMv7 Cortex-A and Cortex-R software and are administered globally through Prometric test centers. Universities and training partners can participate in the program by preparing students and becoming listed on the AAE website. Individuals and employers both benefit through differentiated skills validation and a consistent benchmark for recruitment respectively.
AAME ARM Techcon2013 003v02 Software DevelopmentAnh Dung NGUYEN
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This document provides an overview of the Keil MDK development tools and environment for software development on ARM Cortex-M microcontrollers. It describes the μVision IDE, ARM compiler, debugger and other tools. It discusses the embedded development process, including considerations when moving from a development environment to a standalone application such as memory maps, application startup, and C library usage. It also covers optimization levels, language support, variable types, and default memory maps and C libraries provided by the tools.
The document discusses techniques for optimizing code for multi-processor systems. It covers topics like multi-processing support using symmetric and asymmetric multi-processing, interrupt handling using the Generic Interrupt Controller, power saving modes like standby, shutdown and dormant, and coding techniques to improve performance like avoiding pointer aliasing, optimizing loops, and using the restrict keyword. Specific examples are provided to illustrate optimizations for loops, pointer usage, and entering low power modes.
AAME ARM Techcon2013 006v02 Implementation DiversityAnh Dung NGUYEN
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This document discusses various Cortex-M series processors including the Cortex-M0, Cortex-M0+, Cortex-M3, and Cortex-M4. It describes their architecture, configuration options, and debug features. The Cortex-M0 is a 32-bit processor with optional debug and a 12-25K gate count. The Cortex-M0+ offers improvements like a 2-stage pipeline and optional MPU. The Cortex-M3 and M4 have additional options like an MPU and ETM. Debugging support includes breakpoints, watchpoints, and optional trace modules.
This document discusses ARM instruction sets. It covers topics like ARM and Thumb instruction sets, assembler syntax, data processing instructions, memory access instructions, branch instructions, and instructions for loading constants. It provides details on different instruction types, their syntax, functionality and examples.
The document discusses the evolution of programming languages from machine languages to higher-level languages. It begins with an overview of the three main categories: machine languages, assembly languages, and higher-level languages. It then provides more details on each category, explaining that machine languages use binary, assembly languages use cryptic phrases, and higher-level languages use more English-like syntax. It specifically discusses third-generation languages as the first to use true English phrases.
This document discusses developing code for ARM targets. It covers compilation tools like setting optimization levels and instruction set selection. It also discusses linking and libraries, including static vs dynamic libraries and the C library. The document outlines considerations for different target platforms like development boards and final hardware. It covers debugging methods, including invasive techniques like stopping execution and non-invasive performance monitoring.
This document discusses the C programming language and data structures. It covers the basic structure of C programs, including functions, main functions, and sections like documentation, definitions, declarations, and subprograms. It also discusses basic C programs, data types, operators, control structures, arrays, pointers, structures, unions, and file I/O. The document is intended to introduce students to C language concepts and data structures.
Advanced debugging on ARM Cortex devices such as STM32, Kinetis, LPC, etc.Atollic
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Learn more on advanced debugging of ARM Cortex devices, including how to analyse crashed system after a hard fault exception, SWV real-time event and data tracing, analysing execution history using ETM instruction tracing, dual-core debugging, kernel aware RTOS debugging, and more. Also, learn how to introducing bugs in the first place with static source code analysis (such as MISRA-C), code complexity analysis, and source code review meetings (peer review)
The document provides an overview of ARM processor architectures. It discusses ARM's range of RISC processor core designs including early processors like ARM7TDMI and ARM9TDMI. It covers the evolution of architectures like ARMv6, ARMv7, and ARMv7-M. It provides details on Cortex processor families like Cortex-A, Cortex-R, and Cortex-M. It describes features of various Cortex processors including pipeline stages, memory systems, and instruction sets. The document is intended to introduce the reader to ARM architectures and processor families.
This document provides an overview of memory systems and caching in ARM processors. It discusses memory hierarchies including tightly coupled memory. It covers concepts like alignment, endianness, memory ordering models, and the virtual memory system architecture (VMSA) used in Cortex-A processors. It describes the memory protection unit (MPU) and how it provides memory protection. It also discusses caching in Cortex-A processors including cache terminology, how data is stored in caches, and an example of a memory access involving the cache.
The document describes the ARMv7-A architecture and its support for large physical addresses (LPAE) in Linux. Key points include:
- ARMv7-A supports LPAE through a 3-level translation table that maps 40-bit virtual addresses to 40-bit physical addresses.
- Linux implements LPAE by modifying page table definitions, extending the swapper page directory to cover three levels, and adapting functions for setting page table entries and switching address spaces.
- Low memory is mapped with 2MB sections while page tables can be allocated from high memory. Exception handling and PGD allocation/freeing were also updated for LPAE.
2. Outline
? 軟體工程的重要性
? 實務上的進行方法
Luba Tang (唐文力)
Senior Engineer in CTO/CIT, MediaTek
HW/SW Co-Simulation, Embedded Compiler
3. SW is more costly than HW
? In recent 5 years, software is 3 times costly than hardware
? Software aspects of IC design can now account for 80% or
more of embedded systems development cost
5. Challenges in Modern Embedded Software
? Implement a large, various and variant embedded system
? Shrinking time-to-market for short life cycle of a product
? 10~15 months for releasing
? 6~12 months for being on the shelf
? Changing requirement
? x2 new devices per 10 months
? Coordinate with more than 6 teams coming from different
backgrounds
? Heavy workload
? 250 K Line of code for self product
? 1M Line of code in total system
? High reliability
40. Dependency Checking
? 最常見 dependency checker 為 ./configure script
? Dependency checker 產生器有 Open Source 的
– Autoconf
– Cmake
? Dependency checker 會 Top-down 的檢查函式庫
版本以及系統環境
程式或
Is v2? 函式庫 Is v6?
Is v3?
stdlib Qt math
41. Global Version
? 解決太舊的問題
? 將所有的project設定一個版次號碼
? 規定所有的 dependant的版次必須要小於等於host的版次
? 最上層的dependant為global version
Global version Main
V2
Qt Math
V5 V3
Stdlib
V6
Pthread
V7
42. Local Version
? 解決太新的問題
? 這是從尐數客戶擴張到多數客戶的關鍵
開分支 (branch)
需要 version 3
Host Host Host
Dependant
V3 V3-1 V3-2
合併 (merge)
版次跳躍
Host Host Host
V4 V5 V6
43. Version Threads
2.3-1 2.3-2
Local Versions
2.3
2.4-1
2.4
2.5
2.6-1
2.6
2.7
Global Versions
45. Software Versioning
?功用
– 對外做為看板,告知客戶目前專案的stage of
life cycle
– 對內做為進度管理,得知目前release status
? Point release
? Major release
46. Stage of Life Cycle
2
In House
Beta
5
Customer
testing GA
1
Alpha Success in
Market
4
Internal
testing RTM
0
Pre-alpha Release to
Market
3
developing
RC
Release
Candidate In Market
47. Release Status
? Point release
– 為了bug-fix經常且快速的release
? Major release
– 為了new feature告知客戶應做更新
2.6 2.6.1 2.6.1
2.7 2.6.1
major 2.8 2.6.1 2.6.1 2.9
point
48. Case Study 1 – DirectFB
? Format
– [Major].[Minor].[Micro].[IF_Age].[Bin_Age]
? Major release
– [Major].[Minor]
? Point release
– [Micro]
? Release Status
– [IF Age].[Bin Age]
? Release的規則不固定,隨喜好進版。
? 進版規則
– Existing interface changed => IF Age = 0
– Binary interface changed => Bin Age = 0
– Bug-fixed or new feature => Micro += 1
49. Case Study 2 – Linux Kernel 2.6.11+
? Format
– [Major].[Patch Level].[Minor].[Bug-fixed]
? 改進以往 release方式(2.odd/2.even),利用多個
source tree來增加patch進入mainline的效率
Source tree Versioning Meaning
Mainline 2.6.X/2.6.X-rcY Developing source tree
Stable 2.6.X.Y For bug-fix
Legacy 2.6.X.Y-1 1 version old stable
Mm Integration tree, for new feature
Ck/Rt Improve performance
50. Linux kernel version threads
2.6.11.1 2.6.11.2
stable
2.6.11
2.6.12.1
2.6.12
2.6.13
2.6.14.1
2.6.14
2.6.15
MM Mainline