Synchronous counters
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This document describes different types of synchronous counters that are triggered by a common clock signal. It discusses binary counters that count up in binary, up-down binary counters that can count up or down, BCD counters that count in decimal, and binary counters that can be parallel loaded. The key aspects covered are how the flip-flops are triggered in each counter type and the inputs and functions that control counting direction, clearing, loading, and counting.
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Synchronous counters
- 2. Synchronous Counter Clock pulses are applied to the input of all flip-flops. Common clock trigger all flip-flops simultaneously T=0 or J=K=0 (flip-flop does not change state) T=1 or J=K=1 (flip-flop complements)
- 3. Types of Synchronous Counters Binary Counter Up-Down Binary Counter BCD Counter Binary Counter with Parallel Load
- 4. a. Binary Counter The flip-flop in the least significant position is complemented in every pulse. A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1. If J and K = 0 (state of the counter does not change), however if it is = 1 counter is enabled.
- 5. b. Up-Down Binary Counter A synchronous countdown binary counter goes through the binary states in reverse order. A bit in any other position is complemented if all lower significant bits are equal to 0. Up input = 1 (circuit counts up), Down input = 1 (circuit counts down). Both inputs = 0 (circuit does not change), however if it is = 1 (circuit counts up).
- 6. c. BCD Counter A BCD counts in binary-coded decimal from 0000 to 1001 and back to 0000. Because of the return to 0 after a count of 9. Output Y is equal to 1 when the present state is 1001. Y can enable the count of the next higher significant decade while the same pulse switches the present decade from 1001 to 0000. The unused states for minterms 10 to 15 are taken as dont-care terms. The simplified functions are: T Q1 = 1 T Q2 = Q8 Q1 T Q4 = Q2 Q1 T Q8 = Q8 Q1 + Q4 Q2 Q1 Y = Q8 Q1
- 7. d. Binary Counter with Parallel Load Counters employed in digital systems often require a parallel load capability for transferring an initial binary number into the counter prior to the count operation. When equal to 1, the input load control disables the count operation and causes a transfer of data from the four data inputs into the four flip-flops. If both inputs are zero, clock pulses do not change the state of the register.
- 8. FUNCTION TABLE FOR THE COUNTER Clear Clock Load Count Function 0 X X X Clear to 0 1 1 X Load inputs 1 0 1 Count next binary state 1 0 0 No change The four control inputs Clear, Clock, Load, Count determine the next state. Clear input is asynchronous and when equal to 0, causes the counter to be cleared. X symbolize dont care conditions for the other inputs. With the Load and Count inputs both 0, the output do not change.