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![Verilog coding of DEMUX 1X8 using if else statement
module demux(d, sel, z);
input d;
input [2:0] sel;
output [7:0] z;
reg [7:0] z;
always @( d or sel)
begin
if( sel==3'b000)
z[0]=d;
else if( sel==3'b001)
z[1]=d;
else if( sel==3'b010)
z[2]=d;
else if( sel==3'b011)
z[3]=d;
else if( sel==3'b100)
z[4]=d;
else if( sel==3'b101)
z[5]=d;
else if( sel==3'b110)
z[6]=d;
else
z[7]=d;
end
endmodule](https://image.slidesharecdn.com/verilog-coding-of-de-mux-8x1-160216065025/85/Verilog-coding-of-demux-8-x1-1-320.jpg)
![Verilog coding of DEMUX 1X8 using case statement
module demux(d, sel, z);
input d;
input [2:0] sel;
output [7:0] z;
reg [7:0] z;
always @( d or sel)
begin
case(sel)
3'b000 : z[0] = d;
3'b001 : z[1] = d;
3'b010 : z[2] = d;
3'b011 : z[3] = d;
3'b100 : z[4] = d;
3'b101 : z[5] = d;
3'b110 : z[6] = d;
3'b111 : z[7] = d;
endcase
end
endmodule](https://image.slidesharecdn.com/verilog-coding-of-de-mux-8x1-160216065025/85/Verilog-coding-of-demux-8-x1-2-320.jpg)
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MATLAB CODE OF Shifting sequenceRakesh kumar jha
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This MATLAB code demonstrates how to delay and advance a sequence x(n) by a unit k. It prompts the user to input values for p, q, the delay/advance k, and the sequence x(n). It then generates plots with the original x(n) on top and the delayed/advanced sequence ym on bottom, labeling each appropriately. The delay inserts zeros at the beginning of x(n) equal to k. The advance inserts zeros at the end of x(n) equal to k.Matlab implementation of fast fourier transform
Matlab implementation of fast fourier transformRakesh kumar jha
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This document describes MATLAB code that implements the Fast Fourier Transform (FFT) on various signals. It generates 10 Hz and 20 Hz sinusoidal signals, adds and appends the signals, and applies the FFT to analyze the frequency components. Plots of the original and FFT-transformed signals are displayed to visualize the frequency content. The code demonstrates how the FFT can be used to analyze single and combined signals in MATLAB.Verilog code for decoder
Verilog code for decoderRakesh kumar jha
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This document contains two Verilog code modules for a 3x8 decoder. The first module uses assign statements to decode the inputs a, b, and c into the 8-bit output z. The second module uses not, and gates to decode the inputs into the output in an alternative coding style. Both modules take in the 3-bit input and output the 8-bit decoded value.VERILOG CODE FOR Adder
VERILOG CODE FOR AdderRakesh kumar jha
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The document contains Verilog code for half adders and full adders. It provides two implementations for each: a half adder is implemented using either XOR and AND gates, or XOR and AND modules; a full adder is implemented using XOR, AND and OR gates arranged in a specific way to calculate the sum and carry outputs, or using XOR, AND and OR modules and a wire to decompose the calculation into steps.Reversible code converter
Reversible code converterRakesh kumar jha
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Researchers like Landauer and Bennett have shown that every bit of information lost will generate kTlog2 joules of
energy, whereas the energy dissipation would not occur, if computation is carried out in a reversible way. k is
Boltzmanns constant and T is absolute temperature at which computation is performed. Thus reversible circuits will be
the most important one of the solutions of heat dissipation in Future circuit design. Reversible computing is motivated
by the Von Neumann Landauer (VNL) principle, a theorem of modern physics telling us that ordinary irreversible logic
operation which destructively overwrite previous outputs)in cur a fundamental physics) that performance on most
applications within realistic power constraints might still continue increasing indefinitely. Reversible logic is also a
core part of the quantum circuit modelUjt
UjtRakesh kumar jha
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The unijunction transistor (UJT) is a three-terminal semiconductor device with a single PN junction. It exhibits a negative resistance characteristic, which makes it useful for oscillator circuits. The UJT consists of a lightly doped N-type silicon bar with a single P-type region forming the emitter junction. It has three terminals - base 1, base 2, and emitter. In its active mode, the UJT shows negative resistance, where increasing the emitter voltage initially causes the emitter current to decrease. This physical phenomenon is called conductivity modulation and is caused by injection of holes from the emitter into the base, decreasing the resistance between the emitter and base 1.Pin diode
Pin diodeRakesh kumar jha
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PIN diode consists of heavily doped P and N regions separated by a wide intrinsic region. The wide intrinsic region makes the PIN diode suitable for attenuators, fast switches, photo detectors, and high voltage power electronics applications. PIN diode works as an ordinary PN junction diode up to 100 MHZ, above which it ceases rectification and behaves as a switch or variable resistor. In reverse bias it acts as a capacitor, while in forward bias it acts as a variable resistor whose value decreases with increasing voltage. PIN diodes are used in RF and dc controlled microwave switches, RF and variable attenuators, limiter circuits, photo detectors, and RF modulator circuits.Schottky diode
Schottky diodeRakesh kumar jha
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This document discusses the Schottky diode, a semiconductor diode with a low forward voltage drop and very fast switching speeds. It forms a metal-semiconductor junction, using a metal like molybdenum or platinum in contact with an N-type semiconductor like silicon. This creates a Schottky barrier and results in fast switching without the charge storage and recovery time of a conventional PN junction diode. Key advantages are voltage drops as low as 0.15V, no reverse recovery time, and operation at frequencies from MHz to GHz. Applications include rectification, switching, and protection circuits.Verilog coding of demux 8 x1
- 1. Verilog coding of DEMUX 1X8 using if else statement module demux(d, sel, z); input d; input [2:0] sel; output [7:0] z; reg [7:0] z; always @( d or sel) begin if( sel==3'b000) z[0]=d; else if( sel==3'b001) z[1]=d; else if( sel==3'b010) z[2]=d; else if( sel==3'b011) z[3]=d; else if( sel==3'b100) z[4]=d; else if( sel==3'b101) z[5]=d; else if( sel==3'b110) z[6]=d; else z[7]=d; end endmodule
- 2. Verilog coding of DEMUX 1X8 using case statement module demux(d, sel, z); input d; input [2:0] sel; output [7:0] z; reg [7:0] z; always @( d or sel) begin case(sel) 3'b000 : z[0] = d; 3'b001 : z[1] = d; 3'b010 : z[2] = d; 3'b011 : z[3] = d; 3'b100 : z[4] = d; 3'b101 : z[5] = d; 3'b110 : z[6] = d; 3'b111 : z[7] = d; endcase end endmodule