Clock Skew 2
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Clock skew refers to differences in the arrival times of a clock signal at different flip-flops. Clock skew is caused by differences in delays along the paths from the clock generator to each flip-flop due to factors like wire lengths, gates, and clock edge inversion. The amount of clock skew affects calculations for the maximum clock frequency and allowable clock skew depends on the minimum setup and hold times of the flip-flops.
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Clock Skew 2
- 1. Clock Skew
- 2. Clock Skew If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the amount of clock skew . Clock skew is due to different delays on different paths from the clock generator to the various flip-flops. Different length wires (wires have delay) Gates (buffers) on the paths Flip-Flops that clock on different edges (need to invert clock for some flip-flops) Gating the clock to control loading of registers (a very bad idea)
- 3. Example (Effect of clock skew on clock rate) Clock C2 skewed after C1 T W max T PFF + max t OR + t su (if clock not skewed, i.e., t INV = 0) T W max T PFF + max t OR + t su - min t INV (if clock skewed, i.e., t INV > 0)
- 4. Clock C1 skewed after C2 T W max T PFF + max t OR + t su (if clock not skewed, i.e., t INV = 0) T W max T PFF + max t OR + t su + max t INV (if clock skewed, i.e., t INV > 0)
- 5. Summary of maximum clock frequency calculations C2 skewed after C1: T W max T PFF + max t NET + t su - min t INV C2 skewed before C1: T W max T PFF + max t NET + t su + max t INV
- 6. Example For each of the following two connections find The minimum clock period The maximum and minimum delay from CLK to YOUT
- 7. Circuit 1: max t PFF + max t QY + (n-2) max t XY +max t XD + t su max t PFF + max t QD + t su n 2 Tw Tw T W Minimum Clock Period: Maximum Delay: Minimum Delay: T CY T CY max t PFF + max t QY + (n-1) max t XY min t PFF + min t QY
- 8. Circuit 2: n 2 max t PFF + max t XD + t su max t PFF + max t QD + t su Tw Tw Minimum Clock Period: Maximum Delay: Minimum Delay: T CY T CY max t PFF + max ( max t XY , max t QY ) min t PFF + min ( min t XY , min t QY )
- 9. 13.2. Maximum Allowable Clock Skew How much skew between C1 and C2 can be tolerated in the following circuit? Case 1: C2 delayed after C1 t PFF > t h + t SK t SK < min t PFF - t h
- 10. Case 2: C1 delayed from C2 13.
- 11. How does additional delay between the flip-flops affect the skew calculations? 13. t SK min t PFF - t h t sk min t PFF + min t MUX - t h
- 12. Summary of allowable clock skew calculations 13. t SK + t h t PFF + t NET t SK min t PFF + min t NET - t h
- 13. Example: What is the minimum clock period for the following circuit under the assumption that the clock C2 is skewed after C1 (i.e., C2 is delayed from C1)? 13.
- 14. First calculate the maximum allowable clock skew. Next calculate the minimum clock period due to the path from Q1 to D2. Finally calculate the minimum clock period due to the path from Q2 to D1 t SK < min t PFF + min t N1 - t h T W > max t PFF + max t N1 + t su - min t SK T W > max t PFF + max t N2 + t su + max t SK T W > max t PFF + max t N2 + t su + (min t PFF + min t N1 - t h ) T W > max t PFF + min t PFF + max t N2 + min t N1 + t su - t h N 1 N 2 C 1 C 2 Q 1 D 2 Q 2 D 1 D Q Q D Q Q
- 15. Global Setup Time, Hold Time and Propagation Delay Global setup and hold times (data delayed) T SU = t su + max t NET T H = t h - min t NET
- 16. Global setup & hold time (clock delayed) T SU = t su - min t C T H = t h + max t C
- 17. Global setup & hold time (data & clock delayed) T SU = t su + max t NET - min t C T H = t h - min t NET + max t C
- 18. Global propagation delay T P = t C + t FF + t NET
- 19. Example Find T SU and T H for input signal LD relative to CLK. T SU = t su +max t NET - min t C T H = t h - min t NET + max t C = t su + max t INV + max t NAND + max t NAND - min t INV = t h - min t NAND - min t NAND + max T INV
- 20. Tips & Tricks Use timing diagrams to determine the timing properties of sequential circuits Pitfalls Using typical timing values from the data sheet (use only max and/or min values) Gating the clock
- 21. Review How the flip-flop and gate timing parameters affect the maximum possible clock frequency. How clock skew affect maximum possible clock frequency. How the delay of logic between flip-flops affects the maximum allowable clock skew. How flip-flop setup and hold times are translated by the combinational logic delays to get global setup and hold times.
- 22. THANK YOU