Ch8 lecture slides Chenming Hu Device for ICChenming Hu
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The document discusses bipolar junction transistors (BJTs). It begins by stating that BJTs are still preferred for some high-frequency and analog applications due to their high speed and power output, despite MOS technology eroding their early dominance since 1970. It then provides information on the basic operation and characteristics of BJTs, including definitions of terms like bipolar (referring to both holes and electrons conducting current), collector current, current gain, and how the current gain is affected by factors like emitter doping concentration and bandgap narrowing effects. It also discusses the Ebers-Moll model for describing BJT operation in both the active and saturation regions.
CMOS (complementary metal oxide semiconductor) technology continues to be the
dominant technology for fabricating integrated circuits (ICs or chips). This dominance
will likely continue for the next 25 years and perhaps even longer. Why? CMOS
technology is reliable, manufacturable, low power, low cost, and, perhaps most
importantly, scalable. The fact that silicon integrated circuit technology is scalable was
observed and described in 1965 by Intel founder Gordon Moore. His observations are
now referred to as Moore's law and state that the number of devices on a chip will double
every 18 to 24 months. While originally not specific to CMOS, Moore's law has been
fulfilled over the years by scaling down the feature size in CMOS technology. Whereas
the gate lengths of early CMOS transistors were in the micrometer range (long-channel
devices) the feature sizes of current CMOS devices are in the nanometer range
(short-channel devices).
To encompass both the long- and short-channel CMOS technologies in this book,
a two-path approach to custom CMOS integrated circuit design is adopted. Design
techniques are developed for both and then compared. This comparison gives readers
deep insight into the circuit design process. While the square-law equations used to
describe MOSFET operation that students learn in an introductory course in
microelectronics can be used for analog design in a long-channel CMOS process they are
not useful when designing in short-channel, or nanometer, CMOS technology. The
behavior of the devices in a nanometer CMOS process is quite complex. Simple
equations to describe the devices' behavior are not possible. Rather electrical plots are
used to estimate biasing points and operating behavior. It is still useful, however, for the
student to use mathematical rigor when learning circuit analysis and design and, hence,
the reason for the two-path approach. Hand calculations can be performed using a
long-channel CMOS technology with the results then used to describe how to design in a
nano-CMOS process.